Abstract: Due to the low power consumption, CMOS structures are preferred for creating large and ultra-large integrated circuits. However, the reliability of the circuits is largely limited by the latch phenomenon that occurs in CMOS structures. The electrical characteristic of the latch up phenomenon in a CMOS integrated circuit is characterized by the presence of a number of anomalous phenomena. These effects distort and make ambiguous the results of measuring the electrical sensitivity of the circuits to the latch. The development of microelectronics is constantly striving to reduce the size of the elements of integrated circuits, in particular transistors. Reducing the size of integrated circuits leads to the amplification of short-channel effects in MOS transistors. When reducing the size of integral elements, various options for scaling devices with a metal-oxide-semiconductor structure are considered. The mechanisms that cause the appearance of the snap-in do not depend on the conductivity type of the semiconductor region of the pocket.

Abstract: The greatest success of ion implantation has been achieved in the field of planar technology of semiconductor devices and integrated circuits. The development of devices with elements of nanoparticles, including the active region of which are metal nanoparticles in a dielectric matrix, has been greatly developed. The aim of the work is to simulate the process of ion implantation of a structure consisting of gold nanoparticles in a silicon dioxide matrix and calculations of the distribution of doping ions, cascades of displaced matrix ions and nanoparticles, as well as the distribution of ions reflected from the nanoparticles. The implantation conditions vary depending on the position of the projection of a point on the surface of the structure on the horizontal radius of the nanoparticle from the center to the periphery. A physical model of the process of ion implantation of gold nanoparticles located in a silicon dioxide matrix has been compiled. The process of ionic doping of the structure with boron and arsenic ions was simulated for different cross sections, and graphs of the distribution of doping ions, recoil atoms, reflected and sputtered ions were obtained depending on the coordinate from the center of the nanoparticle.

Abstract: Aluminum and its alloys are the main metallization materials. With an increase in degree of integration the role of interconnections rises: they occupy a growing area of the crystal, the density of the package increases, which leads to a decrease in the thickness and width of the conductive tracks. In nanodimensional structures the value of the current density sufficient for the development of electromigration effects occurs at currents of 50-100 mA. The article explores the factors affecting the mechanism of destruction of the integrated circuits' metallization due to electromigration. The author studies metallization lines at different stages of their destruction by electromigration with the help of raster scanning and transmission electron microscopes. In general, the main problem associated with high-temperature application of aluminum metallization is the large grain size and surface roughness, which makes alignment on such a metal layer difficult. The results of the experiments lead to the conclusion that geometric factors play a dominant role in the mechanism of destruction of metallization of integrated circuits due to electromigration.

Abstract: Aluminium with its alloys is the basic material of integrated circuits metallization. Use of VLSIC toughens the requirements to the parameters of metallization, which determine its reliability, such as surface resistance, step coating quality, number and sizes of tension-caused voids, and electromigration tolerance. Poor quality of metallization is one of the most dangerous defects in semiconductor technology of integrated circuits. Electromigration can cause failure when passing high-density current through metallization. The materials have been tested in order to estimate the intensity of metal resistance variation caused by electromigration. Based on the results of these tests, the authors conclude that geometrical factors play a dominant role in the mechanism of erosion of integrated circuits metallization caused by electromigration. With regard to the tests, the authors formulate recommendations about the transition from the sputtering technique to evaporation deposition. 

Abstract: Silicon-on-sapphire structures serve as a base for the production of radiation-resistant integration circuits, which are very important for space industry, nuclear energetics, and the military sphere. The authors study the silicon-on-sapphire hetero-epitaxial mechanism for the subsequent creation of low-defectiveness transistor structures. Using the Rutherford backscattering, the authors study epitaxial layers of silicon, grown on sapphire substrate. Using the Auger analysis, the authors define the composition and the depth of the transitional layer of silicon-sapphire. The authors ascertain that silicon-to-sapphire bond is performed through tetrahedral sited oxygen. Defectiveness growth can be observed in the regions of spectrum of epitaxial layers, corresponding to the transitional region between the silicon layer and the sapphire substrate, and contributing to ion channeling. Account of an irregular character of the silicon-sapphire transition allows establishing causal link between the charge on the silicon-on-sapphire structure border and leakage current of field emission transistor. The authors develop the method of creation of a semiconductor device with improved parameters both in leakage currents and in structure defects density.